I believe set up time and hold time problems must occur for dummy done. Is there a risk for metastability as well for dummy done because output valid is only high between 2 rising edges (from t=2 to t=3). When output valid goes high for one clock cycle, dummy done is pulled high one cycle later. Is there a risk of metastability for b_box component? Would it be better if b_box enable is kept high for 2 clock cycles as it can miss the enable signal in its process code, I think? Signal output_bb : std_logic_vector(31 downto 0) Īt t=1, b_box enable goes high, at the same time inputs are provided to it. Signal output_valid_bb : std_logic := '0' Signal input_2_bb : std_logic_vector(31 downto 0)
Signal input_1_bb : std_logic_vector(31 downto 0) Output : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) Input_2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0) Input_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0) It takes 2 inputs and when enabled, one clock cycle later it sets the output and pulls high its output valid pin for one cycle.
I have a black box component (no implementation of it, I just made it up and it is only sequential, no combinational part and it only uses the rising edge of the clock in its process part) and in a dummy module I use that module.
It does not make sense in terms of functionality, but what I focus on is the timing of it. I devised an example and drew a timing diagram and I would like to ask some question regarding it all of them are about the same issue. Timing, especially in sequential logic, confuses me a lot.
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